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SOI-enabled three-dimensional integrated-circuit technology

October 11, 2010
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2010 IEEE Int. SOI Conf., 11 October 2010.
Topic:
integrated circuit
R&D area:

Summary

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 ?m and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-siliconvia (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.
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Summary

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a...

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SOI-enabled three-dimensional integrated-circuit technology

Three-dimensional integration technology for advanced focal planes

December 1, 2009
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Conference Paper
Author:
Craig L. Keast
…
Published in:
Mater. Res. Soc. Symp., Volume 1112, 1-5 December 2008, 1112-E01-02.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
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Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...

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Three-dimensional integration technology for advanced focal planes

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

September 28, 2009
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Conference Paper
Author:
Chang-Lee Chen
…
Published in:
3DIC 2009, IEEE Int. Conf. on 3D System Integration, 28-30 September 2009.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-um pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
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Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...

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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography

February 26, 2008
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Conference Paper
Author:
Jeffrey M. Knecht
…
Published in:
SPIE Vol. 6924, Optical Microlithography XXI, 26-27 February 2008, pp. 69244R.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing noncompliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.
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Summary

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE)...

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Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
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Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition

October 1, 2002
  |
Journal Article
Author:
Brian M. Tyrrell
…
Published in:
J. Microlith., Microfab., Microsyst., Vol. 1, No. 3, October 2002, pp. 243-252.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1,0.3, thus enabling 90 nm node lithography with high-numerical aperture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
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Summary

The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently...

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Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition
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