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Gigahertz (GHz) hard X-ray imaging using fast scintillators

September 26, 2013
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Conference Paper
Author:
Zhehui Wang
…
Published in:
SPIE Vol. 8852, Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XV, 26 September 2013, 88521A.
Topic:
optics
R&D area:
R&D group:

Summary

Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard X-ray imaging and achieve an inter-frame time of elss than 10 ns. The time responses and light yield of LYSO, LaBr3, BaF2 and ZnO are measured using an MCP-PMT detector. Zinc Oxide (ZnO) is an attractive material for fast hard X-ray imaging based on GEANT4 simulations and previous studies, but the measured light yield from the samples is much lower than expected.
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Summary

Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard X-ray imaging and achieve an inter-frame time of elss than 10 ns. The time responses and light yield...

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Gigahertz (GHz) hard X-ray imaging using fast scintillators

A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

February 9, 2009
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
ISSCC 09, 2009 IEEE Int. Solid-State Circuits Conf., 8-12 February 2009, pp. 38-39.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.
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Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications...

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A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

A 64 x 64-pixel CMOS test chip for the development of large-format ultra-high-speed snapshot imagers

September 1, 2008
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Journal Article
Author:
Robert Berger
…
Published in:
IEEE J. Solid-State Circuits, Vol. 43, No. 9, September 2008, pp. 1940-1950.
Topic:
sensors
R&D area:
R&D group:

Summary

A 64 x 64-pixel test circuit was designed and fabricated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit performance, test structures are periodically located throughout the 64 x 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than +-3 ps and jitter that is less than +-1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.
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Summary

A 64 x 64-pixel test circuit was designed and fabricated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution...

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A 64 x 64-pixel CMOS test chip for the development of large-format ultra-high-speed snapshot imagers

Back-illuminated three-dimensionally integrated CMOS image sensors for scientific applications

August 27, 2007
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
SPIE Vol. 6690, Focal Plane Arrays for Space Telescopes III, 27-28 August 2007, 669009.
Topic:
sensors
R&D area:
R&D group:

Summary

SOI-based active pixel image sensors have been built in both monolithic and vertically interconnected pixel technologies. The latter easily supports the inclusion of more complex pixel circuitry without compromising pixel fill factor. A wafer-scale back-illumination process is used to achieve 100% fill factor photodiodes. Results from 256 x 256 and 1024 x 1024 pixel arrays are presented, with discussion of dark current improvement in the differing technologies.
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Summary

SOI-based active pixel image sensors have been built in both monolithic and vertically interconnected pixel technologies. The latter easily supports the inclusion of more complex pixel circuitry without compromising pixel fill factor. A wafer-scale back-illumination process is used to achieve 100% fill factor photodiodes. Results from 256 x 256 and...

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Back-illuminated three-dimensionally integrated CMOS image sensors for scientific applications

Lincoln Laboratory high-speed solid-state imager technology

September 17, 2006
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Conference Paper
Author:
Robert K. Reich
…
Published in:
SPIE Vol. 6279, 27th Int. Congress on High-Speed Photography and Photonics, 17-22 September 2006, 62791K.
Topic:
optics
R&D area:
R&D group:

Summary

Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 ¿ 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames per second with readout noise of less than 10 e- rms. An electronic shutter has been integrated into the pixels of the back-illuminated (BI) CCD imagers that give snapshot exposure times of less than 10 ns. For burst imaging, a 5 cm x 5 cm, 512 x 512-element, multi-frame CCD imager that collects four sequential image frames at megahertz rates has been developed for the Los Alamos National Laboratory Dual Axis Radiographic Hydrodynamic Test (DARHT) facility. To operate at fast frame rates with high sensitivity, the imager uses the same electronic shutter technology as the continuously framing 128 x 128 CCD imager. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with ultra-short exposure times (100 to 300 ps). The detector will consist of CMOS readouts for high speed sampling (tens of picoseconds transistor switching times) that are bump bonded to deep-depletion silicon photodiodes. A 64 x 64-pixel CMOS test chip has been designed, fabricated and characterized to investigate the feasibility of making large-format detectors with short, simultaneous exposure times.
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Summary

Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 ¿ 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames...

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Lincoln Laboratory high-speed solid-state imager technology

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
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Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

Dynamic response of an electronically shuttered CCD imager

June 1, 2004
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Journal Article
Author:
Dennis D. Rathman
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Published in:
IEEE. Trans. Electron Devices, Vol. 51, No. 6, June 2004, pp. 864-869.
Topic:
sensors
R&D area:
R&D group:

Summary

The dynamic response of an electronically shuttered charge-coupled device (CCD) imager to nanosecond voltage pulses has been investigated. Measurements show that the shutter can be dynamically opened and closed in nanosecond times. For the shutter opening, simulations indicate that the collection of photoelectrons occurs in times much shorter than that needed to form the steady-state depletion region under the CCD well. In addition, the shutter closing occurs faster than the reconstitution of the p-buried (shutter) layer. Simulations further indicate that electric fields created in the neutral substrate by the shutter clocks enable photogenerated charge collection/rejection on nanosecond time scales despite the fact that the depletion-region formation and collapse take much longer times.
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Summary

The dynamic response of an electronically shuttered charge-coupled device (CCD) imager to nanosecond voltage pulses has been investigated. Measurements show that the shutter can be dynamically opened and closed in nanosecond times. For the shutter opening, simulations indicate that the collection of photoelectrons occurs in times much shorter than that...

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Dynamic response of an electronically shuttered CCD imager

High-fill-factor, burst-frame-rate charge-coupled device

August 3, 2003
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Conference Paper
Author:
Robert K. Reich
…
Published in:
SPIE Vol. 5210, Ultrahigh- and High-Speed Photography, Photonics, and Videography, 3-8 August 2003, pp. 95-104.
Topic:
electronics
R&D area:
R&D group:

Summary

A 512x512-element, multi-frame charge-coupled device (CCD) has been developed for collecting four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology developed for back-illuminated CCDs. Device-level simulations were done to estimate the CCD collection well spaces for sub-microsecond photoelectron collection times. Also required for the high frame rates were process enhancements that included metal strapping of the polysilicon gate electrodes and a second metal layer. Tests on finished back-illuminated CCD imagers have demonstrated sequential multi-frame capture capability with integration intervals in the hundreds of nanoseconds range.
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Summary

A 512x512-element, multi-frame charge-coupled device (CCD) has been developed for collecting four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology developed for back-illuminated CCDs. Device-level simulations were done to estimate the CCD collection well spaces for...

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High-fill-factor, burst-frame-rate charge-coupled device

High-speed, electronically shuttered solid-state imager technology

July 8, 2002
  |
Conference Paper
Author:
Robert K. Reich
…
Published in:
Rev. Sci. Instrum. Vol. 74, No. 3, Pt. II, March 2003, pp. 2027-2031 (Proceedings of the 14th Topical Conference on High-Temperature Plasma Diagnostics, 8-11 July 2002)
Topic:
electronics
R&D area:
R&D group:

Summary

Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cmx5 cm, 512x512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology designed for back-illuminated CCDs. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with short integration times (100 ps to 1 ns). Proposed device architectures use CMOS technology for high speed sampling (tens of picoseconds transistor switching times). Techniques for parallel clock distribution, that triggers the sampling of x-ray photoelectrons, will be described that exploit features of CMOS technology.
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Summary

Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cmx5 cm, 512x512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity...

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High-speed, electronically shuttered solid-state imager technology
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