Publications

Refine Results

(Filters Applied) Clear All

By

Three-dimensional integration technology for advanced focal planes

December 1, 2009
  |
Conference Paper
Author:
Craig L. Keast
…
Published in:
Mater. Res. Soc. Symp., Volume 1112, 1-5 December 2008, 1112-E01-02.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
READ LESS

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...

READ MORE
Three-dimensional integration technology for advanced focal planes

Scaling three-dimensional SOI integrated-circuit technology

October 1, 2007
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2007 IEEE Int. SOI Conf. Proc., 1-4 October 2007, pp. 87-88.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI) circuit fabrication, low-temperature wafer-scale oxide-to-oxide bonding, precision wafer-to-wafer alignment, and dense unrestricted 3D vias interconnecting stacked circuit layers, successfully demonstrated in a large area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible imager. In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +--0.5 am wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a backmetal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.
READ LESS

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...

READ MORE
Scaling three-dimensional SOI integrated-circuit technology

A wafer-scale 3-D circuit integration technology

October 1, 2006
  |
Journal Article
Author:
James A. Burns
…
Published in:
IEEE Trans. Electron Devices, Vol. 53, No. 10, October 2006, pp. 2507-2516.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-[Omega] 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 x 1024 visible imager with an 8-um pixel pitch, and a 64 x 64 Geiger-mode laser radar chip are described.
READ LESS

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...

READ MORE
A wafer-scale 3-D circuit integration technology

Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers

February 6, 2006
  |
Conference Paper
Author:
Brian F. Aull
…
Published in:
ISSCC 2006, IEEE Int. Solid-State Circuits Conf., 6-9 February 2006.
Topic:
ladar
R&D area:
R&D group:

Summary

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit, thereby measuring photon arrival time. This "photon-to-digital conversion" yields quantum-limited sensitivity and noiseless readout, enabling high-performance ladar systems. Previously reported focal planes, based on bump bonding or epoxy bonding the APDs to foundry chips, had coarse (100um) pixel spacing and 0.5ns timing quantization.
READ LESS

Summary

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit...

READ MORE
Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
READ LESS

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

READ MORE
Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

Monolithic 3.3V CCD/SOI-CMOS Imager Technology

December 10, 2000
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
IEEE Int. Eelctron Devices Mtg., 10-13 December 2000, pp. 30.3.1-30.3.4.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm SOI-CMOS ring oscillators have stage delay of 48ps at 3.3V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.
READ LESS

Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm...

READ MORE
Monolithic 3.3V CCD/SOI-CMOS Imager Technology
1-6 of 6