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Germanium CCDs for large-format SWIR and x-ray imaging

May 25, 2017
  |
Journal Article
Author:
Christopher W. Leitz
…
Published in:
J. Instrum., Vol. 12, No. 5, May 2017, C05014.
Topic:
photonics
R&D area:
R&D group:

Summary

Germanium exhibits high sensitivity to short-wave infrared (SWIR) and X-ray radiation, making it an interesting candidate for imaging applications in these bands. Recent advances in germanium processing allow for high-quality charge-coupled devices (CCDs) to be realized in this material. In this article, we discuss our evaluation of germanium as an absorber material for CCDs via fabrication and analysis of discrete devices such as diodes, metal-insulator-semiconductor capacitors, and buried-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We then describe fabrication of our first imaging device on germanium, a 32 x 1 x 8.1 um linear shift register. Based on this work, we find that germanium is a promising material for CCDs imaging in the SWIR and X-ray bands.
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Summary

Germanium exhibits high sensitivity to short-wave infrared (SWIR) and X-ray radiation, making it an interesting candidate for imaging applications in these bands. Recent advances in germanium processing allow for high-quality charge-coupled devices (CCDs) to be realized in this material. In this article, we discuss our evaluation of germanium as an...

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Germanium CCDs for large-format SWIR and x-ray imaging

Radiation effects in 3D integrated SOI SRAM circuits

December 1, 2011
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Journal Article
Author:
Pascale M. Gouker
…
Published in:
IEE Trans. Nuclear Sci., Vol. 58, No. 6, December 2011, pp. 2845-2854.
Topic:
integrated circuit
R&D area:

Summary

Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated usingMonte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.
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Summary

Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense...

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Radiation effects in 3D integrated SOI SRAM circuits

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

September 28, 2009
  |
Conference Paper
Author:
Chang-Lee Chen
…
Published in:
3DIC 2009, IEEE Int. Conf. on 3D System Integration, 28-30 September 2009.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-um pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
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Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...

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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
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