We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 ?m and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-siliconvia (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.