Publications

Refine Results

(Filters Applied) Clear All

By

Snapshot on-chip HDR ROIC architectures

June 7, 2015
  |
Conference Paper
Author:
Christy F. Cull
…
Published in:
Computational Optical Sensing and Imaging, 7-11 June 2015.
Topic:
optics
R&D area:
R&D group:

Summary

We describe novel digital readout integrated circuits (DROICs) that achieve snapshot on-chip high dynamic range imaging where most commercial systems require a multiple exposure acquisition.
READ LESS

Summary

We describe novel digital readout integrated circuits (DROICs) that achieve snapshot on-chip high dynamic range imaging where most commercial systems require a multiple exposure acquisition.

READ MORE
Snapshot on-chip HDR ROIC architectures

Smart pixel imaging with computational-imaging arrays

July 1, 2014
  |
Conference Paper
Author:
Christy F. Cull
…
Published in:
SPIE, Vol. 9070, Infrared Technology and Applications XL, 5 May 2014, 90703D.
Topic:
sensing
R&D area:
R&D group:

Summary

Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plan array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digital-pixel focal plane array (DFPA) devices for many years. In this work, we leverage legacy designs modified with new features to realize a computational imaging array (CIA) with advanced pixel-processing capabilities. We briefly review the use of DFPAs for on-chip background removal and image plane filtering. We focus on two digital readout integrated circuits (DROICS) as CIAs for two-dimensional (2D) transient target tracking and three-dimensional (3) transient target estimation using per-pixel coded-apertures or flutter shutters. This paper describes two DROICs -- a SWIR pixel-processing imager (SWIR-PPI) and a Visible CIA (VISCIA). SWIR-PPI is a DROIC with a 1 kHz global frame rate with a maximum per-pixel shuttering rate of 100 MHz, such that each pixel can be modulated by a time-varying, pseudo-random, and duo-binary signal (+1,-1,0). Combining per-pixel time-domain coding and processing enables 3D (x,y,T) target estimation with limited loss of spatial resolution. We evaluate structured and pseudo-random encoding strategies and employ linear inversion and non-linear inversion using total-variation minimization to estimate a 3D data cube from a single 2D temporally-encoded measurement. The VISCIA DROIC, while low-resolution, has a 6 kHz global frame rate and simultaneously encodes eight periodic or aperiodic transient target signatures at a maximum rate of 50 MHz using eight 8-bit counters. By transferring pixel-based image plane coding to the DROIC and utilizing sophisticated processing, our CIAs enable on-chip temporal super-resolution.
READ LESS

Summary

Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plan array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digital-pixel focal plane array...

READ MORE
Smart pixel imaging with computational-imaging arrays

Active hyperspectral imaging using a quantum cascade laser (QCL) array and digital-pixel focal plane array (DFPA) camera

June 16, 2014
  |
Journal Article
Author:
Anish K. Goyal
…
Published in:
Opt. Express, Vol. 22, No. 12, 16 June 2014, pp. 14392-14401.
Topic:
lasers
R&D area:
R&D group:

Summary

We demonstrate active hyperspectral imaging using a quantum-cascade laser (QCL) array as the illumination source and a digital-pixel focal-plane-array (DFPA) camera as the receiver. The multi-wavelength QCL array used in this work comprises 15 individually addressable QCLs in which the beams from all lasers are spatially overlapped using wavelength beam combining (WBC). The DFPA camera was configured to integrate the laser light relfected from the sample and to perform on-chip subtraction of the passive thermal background. A 27-frame hyperspectral image was acquired of a liquid contaminant on a diffuse gold surface at a range of 5 meters. The measured spectral reflectance closely matches the calculated reflectance. Furthermore, the high-speed capabilities of the system were demonstrated by capturing differential reflectance images of sand and KClO3 particles that were moving at speeds of up to 10 m/s.
READ LESS

Summary

We demonstrate active hyperspectral imaging using a quantum-cascade laser (QCL) array as the illumination source and a digital-pixel focal-plane-array (DFPA) camera as the receiver. The multi-wavelength QCL array used in this work comprises 15 individually addressable QCLs in which the beams from all lasers are spatially overlapped using wavelength beam...

READ MORE
Active hyperspectral imaging using a quantum cascade laser (QCL) array and digital-pixel focal plane array (DFPA) camera

Simultaneous dynamic pupil coding with on-chip coded aperture temporal imaging

June 13, 2014
  |
Conference Paper
Author:
Christy F. Cull
…
Published in:
SRS 2014: Signal Recovery and Synthesis Conf., 13-17 June 2014.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We describe a new sensor that combines dynamic pupil coding with a digital readout integrated circuit (DROIC) capable of modulating a scene with a global or per-pixel time-varying, pseudo-random, and duo-binary signal (+1-1,0).
READ LESS

Summary

We describe a new sensor that combines dynamic pupil coding with a digital readout integrated circuit (DROIC) capable of modulating a scene with a global or per-pixel time-varying, pseudo-random, and duo-binary signal (+1-1,0).

READ MORE
Simultaneous dynamic pupil coding with on-chip coded aperture temporal imaging

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

May 5, 2014
  |
Conference Paper
Author:
Jeffrey W. Little
…
Published in:
SPIE, Vol. 9070, Infrared Technology and Applications XL, 5 May 2014, 90703B.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10us latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.
READ LESS

Summary

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization...

READ MORE
Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

Pixel-processing imager development for directed energy applications

August 26, 2013
  |
Conference Paper
Author:
Jeffrey W. Little
…
Published in:
Directed Energy Systems Symposium, 26-29 August 2013.
Topic:
lasers
R&D area:
R&D group:

Summary

Tactical high-energy laser (HEL) systems face a range of imaging-related challenges in wavefront sensing, acquiring and tracking targets, selecting the HEL aimpoint, and assessing lethality. Accomplishing these functions in a timely fashion may be limited by competing requirements on total field of regard, target resolution, signal to noise, and focal plane readout bandwidth. In this paper, we explore the applicability of an emerging pixel-processing imager (PPI) technology to these challenges. The on-focal-plane signal processing capabilities of the MIT Lincoln Laboratory PPI technology have recently been extended in support of directed energy applications. We describe this work as well as early results from a new PPI-based short-wave-infrared focal plane readout capable of supporting diverse applications such as low-latency Shack-Hartmann wavefront sensing, centroid computation, and Fitts correlation tracking.
READ LESS

Summary

Tactical high-energy laser (HEL) systems face a range of imaging-related challenges in wavefront sensing, acquiring and tracking targets, selecting the HEL aimpoint, and assessing lethality. Accomplishing these functions in a timely fashion may be limited by competing requirements on total field of regard, target resolution, signal to noise, and focal...

READ MORE
Pixel-processing imager development for directed energy applications

Radiation effects in 3D integrated SOI SRAM circuits

December 1, 2011
  |
Journal Article
Author:
Pascale M. Gouker
…
Published in:
IEE Trans. Nuclear Sci., Vol. 58, No. 6, December 2011, pp. 2845-2854.
Topic:
integrated circuit
R&D area:

Summary

Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated usingMonte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.
READ LESS

Summary

Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense...

READ MORE
Radiation effects in 3D integrated SOI SRAM circuits

SET characterization in logic circuits fabricated in a 3DIC technology

December 1, 2011
  |
Journal Article
Author:
Pascale M. Gouker
…
Published in:
IEEE Trans. Nuclear Sci., Vol. 58, No. 6, December 2011, pp. 2555-2562.
Topic:
integrated circuit
R&D area:

Summary

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-um-thick layer. This 3D technology is extremely will suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-um-wide-through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explaine dby considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material laters of the 3DIC stack. We also show that the backmetal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications.
READ LESS

Summary

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-um-thick layer. This 3D technology is extremely will suited for high-density circuit integration because of the small dimension the...

READ MORE
SET characterization in logic circuits fabricated in a 3DIC technology

Three-dimensional integration technology for advanced focal planes

December 1, 2009
  |
Conference Paper
Author:
Craig L. Keast
…
Published in:
Mater. Res. Soc. Symp., Volume 1112, 1-5 December 2008, 1112-E01-02.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
READ LESS

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...

READ MORE
Three-dimensional integration technology for advanced focal planes

Time delay integration and in-pixel spatiotemporal filtering using a nanoscale digital CMOS focal plane readout

November 1, 2009
  |
Journal Article
Author:
Brian M. Tyrrell
…
Published in:
IEEE Trans. on Electron Devices, Vol. 56, No. 11, November 2009, pp. 2516-2533.
Topic:
image processing
R&D area:
R&D group:

Summary

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 x 256 30-um-pitch detector array. Demonstrated in this paper is the application of this DFPA ROIC architecture to problems of background pedestal mitigation, wide-field imaging, image stabilization, edge detection, and velocimetry. The DFPA architecture is reviewed, and pixel performance metrics are discussed in the context of the application examples. The measured data reported here are for DFPA ROICs implemented in 90-nm CMOS technology and hybridized to HgxCd1-xTe (MCT) detector arrays with cutoff wavelengths ranging from 7 to 14.5 m and a specified operating temperature of 60 K-80 K.
READ LESS

Summary

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 x 256 30-um-pitch detector array. Demonstrated in this...

READ MORE
Time delay integration and in-pixel spatiotemporal filtering using a nanoscale digital CMOS focal plane readout
1-10 of 19