Publications

Refine Results

(Filters Applied) Clear All

Tagged As

X-band receiver front-end chip in silicon germanium technology

January 23, 2008
  |
Conference Paper
Author:
T. K. Quach
…
Published in:
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 23-25 January 2008.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier, lead-lag splitter, balanced amplifiers, double balanced mixer, absorptive filter, and an IF amplifier. The integrated chip achieved greater than 30 dB of gain and less than 6 dB of noise figure.
READ LESS

Summary

This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit...

READ MORE
X-band receiver front-end chip in silicon germanium technology

Design approaches for digitally dominated active pixel sensors: leveraging Moore's law scaling in focal plane readout design

January 20, 2008
  |
Conference Paper
Author:
Brian M. Tyrrell
…
Published in:
SPIE Vol. 6900, Quantum Sensing and Nanophotonic Devices V, 20-23 January 2008, 69000W.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes. Although the front-end design must be optimized to interface with a particular detector, the dominant back end architecture provides considerable potential for design reuse. In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths between 9 and 14.5 um are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS process and implementing a 256 x 256 pixel array on a 30-um pitch. In one of the implemented designs, the feasibility of implementing a 15-um pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal processing allows for a much reduced readout bandwidth requirement with these architectures. To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.
READ LESS

Summary

Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it...

READ MORE
Design approaches for digitally dominated active pixel sensors: leveraging Moore's law scaling in focal plane readout design

Scaling three-dimensional SOI integrated-circuit technology

October 1, 2007
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2007 IEEE Int. SOI Conf. Proc., 1-4 October 2007, pp. 87-88.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI) circuit fabrication, low-temperature wafer-scale oxide-to-oxide bonding, precision wafer-to-wafer alignment, and dense unrestricted 3D vias interconnecting stacked circuit layers, successfully demonstrated in a large area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible imager. In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +--0.5 am wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a backmetal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.
READ LESS

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...

READ MORE
Scaling three-dimensional SOI integrated-circuit technology

A 16mW 8Mbps fractional-n FSK modulator at 15.8-18.9GHz

June 3, 2007
  |
Conference Paper
Author:
Matthew Z. Straayer
…
Published in:
2007 IEEE Radio Frequency Integrated Circuits Symp., 3-5 June 2007, pp. 533-536.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Indirect modulation of fractional-N synthesizers is an energy-efficient architecture capable of moderate data rates, and is well-suited for use in sensor networks or WLAN. Although the architecture is used primarily at low RF frequencies, the capability for fractional- N synthesizers at Ku-band and above currently exist in available silicon technology. Recent demonstrations at 10- 25GHz show promising results, although power consumption at this higher frequency remains high for small batterypowered devices. This work implements a fully-integrated fractional-N synthesizer optimized for power efficient modulation at 15.8 to 18.9GHz with an 80MHz reference. Binary and 4-ary FSK modulation of up to 8Mbps is achieved while consuming 16mW in IBM 0.18um SiGe BiCMOS.
READ LESS

Summary

Indirect modulation of fractional-N synthesizers is an energy-efficient architecture capable of moderate data rates, and is well-suited for use in sensor networks or WLAN. Although the architecture is used primarily at low RF frequencies, the capability for fractional- N synthesizers at Ku-band and above currently exist in available silicon technology...

READ MORE
A 16mW 8Mbps fractional-n FSK modulator at 15.8-18.9GHz

The digital focal plane array (DFPA) architecture for data processing "on-chip"

February 5, 2007
  |
Conference Paper
Author:
Michael W. Kelly
…
Published in:
2007 Meeting of the Military Sensing Symposia (MSS) Specialty Group on Camouflage, Concealment & Deception; Passive Sensors; Detectors; and Materials, 5-9 February 2007.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The digital focal plane array (DFPA) project seeks to develop readout integrated circuits (ROICs) utilizing aggressively scaled and commercially available CMOS. Along with focal plane scaling and readout robustness benefits, the DFPA architecture provides a very simple way to implement processing algorithms directly on image data, in real-time, and prior to read-out of the data to an external digitizer or computer. In principle, almost any linear image processing filter kernel can be convolved with the scene image prior to readout. The useful size of the filter kernel is only limited by the size of the DFPA. Time domain filters can also be implemented on the ROIC to accomplish digital time domain integration (TDI) or change detection algorithms. The unique architecture can achieve the processing capability without the use of traditional digital adders or multipliers, like those used in most signal processors. Instead, a DFPA manipulates sequential digital counters under every pixel in a unique way to achieve the desired functionality. A non-addressable readout scheme is used for data transfer in four possible directions across the array. Although we are currently targeting longwave infrared (LWIR) applications, the approach can be potentially applied to any imaging application in any band.
READ LESS

Summary

The digital focal plane array (DFPA) project seeks to develop readout integrated circuits (ROICs) utilizing aggressively scaled and commercially available CMOS. Along with focal plane scaling and readout robustness benefits, the DFPA architecture provides a very simple way to implement processing algorithms directly on image data, in real-time, and prior...

READ MORE
The digital focal plane array (DFPA) architecture for data processing "on-chip"

A wafer-scale 3-D circuit integration technology

October 1, 2006
  |
Journal Article
Author:
James A. Burns
…
Published in:
IEEE Trans. Electron Devices, Vol. 53, No. 10, October 2006, pp. 2507-2516.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-[Omega] 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 x 1024 visible imager with an 8-um pixel pitch, and a 64 x 64 Geiger-mode laser radar chip are described.
READ LESS

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...

READ MORE
A wafer-scale 3-D circuit integration technology

Ultra-linear superwideband chirp generator using digital compensation

June 11, 2006
  |
Conference Paper
Author:
Matthew Z. Straayer
…
Published in:
IEEE MTT-S Int. Microwave Symp., 11-16 June 2006, pp. 403-406.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

A novel digital compensation technique is applied to linearize the frequency generation of a superwideband chirp. Ultra-linear, low-noise swept local oscillators (SLO) are critical to the two-tone dynamic range performance of compressive receivers. The proposed technique enables full software control of the chirp linearity, slope, and offset to allow automated real-time calibration and testing, including automatic compensation for temperature variation. This approach combines recently available commercial high-speed digital, mixed-signal, and analog integrated circuits along with microwave components to create a 15.5-24 GHz chirp over 60 nsec with
READ LESS

Summary

A novel digital compensation technique is applied to linearize the frequency generation of a superwideband chirp. Ultra-linear, low-noise swept local oscillators (SLO) are critical to the two-tone dynamic range performance of compressive receivers. The proposed technique enables full software control of the chirp linearity, slope, and offset to allow automated...

READ MORE
Ultra-linear superwideband chirp generator using digital compensation

Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

August 3, 2005
  |
Conference Paper
Author:
Michael W. Kelly
…
Published in:
SPIE Vol. 5902. Focal Plane Arrays for Space Telescopes II, 3-4 August 2005, pp. 1-11.
Topic:
sensors
R&D area:
R&D group:

Summary

The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18- micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.
READ LESS

Summary

The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and...

READ MORE
Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
READ LESS

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

READ MORE
Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition

October 1, 2002
  |
Journal Article
Author:
Brian M. Tyrrell
…
Published in:
J. Microlith., Microfab., Microsyst., Vol. 1, No. 3, October 2002, pp. 243-252.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1,0.3, thus enabling 90 nm node lithography with high-numerical aperture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
READ LESS

Summary

The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently...

READ MORE
Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition
21-30 of 31