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Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

June 1, 2015
  |
Journal Article
Author:
Sergey K. Tolpygo
…
Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, June 2015, 1101312.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm^2 to 50 kA/cm^2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes form 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10^6 JJ/cm^2 and 193-nm photolithography for JJ definition are discussed.
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Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10...

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Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

June 1, 2015
  |
Journal Article
Author:
Sergey K. Tolpygo
…
Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, 1 June 2015, 1100905.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities >10^6 Josephson junctions per cm^2 are discussed.
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Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with...

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Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

High dynamic range suppressed-bias microwave photonic links using unamplified semiconductor laser source

September 11, 2012
  |
Conference Paper
Author:
Sivasubramaniam S. Yegnanarayanan
…
Published in:
AVFOP 2012: IEEE Avionics, Fiber-Optics and Photonics Tech. Conf., 11-13 September 2012, pp. 28-9.
Topic:
optics
R&D area:
R&D group:

Summary

Microwave photonic (MWP) links with a low noise figure and high dynamic range are required for antenna remoting, radio-over-fiber (RoF), and other advanced applications. MWP links have recently been demonstrated with noise figures approaching 3 dB, without any electrical preamplification, by using low-noise high-power laser sources in conjunction with efficient optical intensity modulators and high-power photodetectors. An alternate approach to noise figure reduction, suitable for sub-octave links, is based on using a high-power laser source and shifting the bias point of an external optical intensity modulator to reduce the average photocurrent and suppress excess link noise. Here, we report the performance of a novel slab-coupled optical waveguide external-cavity laser (SCOWECL) in a suppressed bias MWP link. We compare the performance of this link with a suppressed-bias link using a source comprising a commercial-off-the-shelf (COTS) laser and erbium-doped fiber amplifier (EDFA) and show that MWP links built using SCOW-based emitter technology offer superior performance due to the small-form factor, high-efficiency, low-noise, and high power laser source.
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Summary

Microwave photonic (MWP) links with a low noise figure and high dynamic range are required for antenna remoting, radio-over-fiber (RoF), and other advanced applications. MWP links have recently been demonstrated with noise figures approaching 3 dB, without any electrical preamplification, by using low-noise high-power laser sources in conjunction with efficient...

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High dynamic range suppressed-bias microwave photonic links using unamplified semiconductor laser source

Impact of semiconductor optical amplifiers in coherent down-conversion microwave photonic links

June 6, 2012
  |
Conference Paper
Author:
Sivasubramaniam S. Yegnanarayanan
…
Published in:
CLEO: Conf. on Lasers and Electro-Optics, 6-11 June 2012.
Topic:
optics
R&D area:
R&D group:

Summary

We compare the impact of conventional semiconductor optical amplifiers (SOAs) and high linearity slab-coupled optical waveguide amplifiers (SCOWAs) on the SFDR of carrier-suppressed coherent down-conversion microwave photonic links.
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Summary

We compare the impact of conventional semiconductor optical amplifiers (SOAs) and high linearity slab-coupled optical waveguide amplifiers (SCOWAs) on the SFDR of carrier-suppressed coherent down-conversion microwave photonic links.

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Impact of semiconductor optical amplifiers in coherent down-conversion microwave photonic links

X-band receiver front-end chip in silicon germanium technology

January 23, 2008
  |
Conference Paper
Author:
T. K. Quach
…
Published in:
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 23-25 January 2008.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier, lead-lag splitter, balanced amplifiers, double balanced mixer, absorptive filter, and an IF amplifier. The integrated chip achieved greater than 30 dB of gain and less than 6 dB of noise figure.
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Summary

This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit...

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X-band receiver front-end chip in silicon germanium technology
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