Publications

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.

Indirect modulation of fractional-N synthesizers is an energy-efficient architecture capable of moderate data rates, and is well-suited for use in sensor networks or WLAN. Although the architecture is used primarily at low RF frequencies, the capability for fractional- N synthesizers at Ku-band and above currently exist in available silicon technology. Recent demonstrations at 10- 25GHz show promising results, although power consumption at this higher frequency remains high for small batterypowered devices. This work implements a fully-integrated fractional-N synthesizer optimized for power efficient modulation at 15.8 to 18.9GHz with an 80MHz reference. Binary and 4-ary FSK modulation of up to 8Mbps is achieved while consuming 16mW in IBM 0.18um SiGe BiCMOS.

This work presents the design and measurement of a 2Mbps BFSK transceiver at 1.35 to 1.75GHz for use in wireless sensor node applications. The receiver is a direct conversion architecture and has a sensitivity of -74dBm at 2Mbps and consumes 8.0mW. The transmitter generates orthogonal BFSK modulation through the use of digital pre-emphasis of the synthesizer frequency control word and consumes 9.7mW including the power amplifier. The transmitter delivers >3dBm of output power for a total transmitter power efficiency of 23% and a transmitter FOM of 4.85nJ/bit at 2Mbps.

A novel digital compensation technique is applied to linearize the frequency generation of a superwideband chirp. Ultra-linear, low-noise swept local oscillators (SLO) are critical to the two-tone dynamic range performance of compressive receivers. The proposed technique enables full software control of the chirp linearity, slope, and offset to allow automated real-time calibration and testing, including automatic compensation for temperature variation. This approach combines recently available commercial high-speed digital, mixed-signal, and analog integrated circuits along with microwave components to create a 15.5-24 GHz chirp over 60 nsec with