Publications
Gigahertz (GHz) hard X-ray imaging using fast scintillators
September 26, 2013
Conference Paper
Published in:
SPIE Vol. 8852, Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XV, 26 September 2013, 88521A.
Summary
Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard X-ray imaging and achieve an inter-frame time of elss than 10 ns. The time responses and light yield of LYSO, LaBr3, BaF2 and ZnO are measured using an MCP-PMT detector. Zinc Oxide (ZnO) is an attractive material for fast hard X-ray imaging based on GEANT4 simulations and previous studies, but the measured light yield from the samples is much lower than expected.
Summary
Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard X-ray imaging and achieve an inter-frame time of elss than 10 ns. The time responses and light yield...
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A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor
February 9, 2009
Conference Paper
Published in:
ISSCC 09, 2009 IEEE Int. Solid-State Circuits Conf., 8-12 February 2009, pp. 38-39.
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Summary
The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.
Summary
The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications...
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A 64 x 64-pixel CMOS test chip for the development of large-format ultra-high-speed snapshot imagers
September 1, 2008
Journal Article
Published in:
IEEE J. Solid-State Circuits, Vol. 43, No. 9, September 2008, pp. 1940-1950.
Summary
A 64 x 64-pixel test circuit was designed and fabricated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit performance, test structures are periodically located throughout the 64 x 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than +-3 ps and jitter that is less than +-1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.
Summary
A 64 x 64-pixel test circuit was designed and fabricated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution...
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Design approaches for digitally dominated active pixel sensors: leveraging Moore's law scaling in focal plane readout design
January 20, 2008
Conference Paper
Published in:
SPIE Vol. 6900, Quantum Sensing and Nanophotonic Devices V, 20-23 January 2008, 69000W.
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Summary
Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes. Although the front-end design must be optimized to interface with a particular detector, the dominant back end architecture provides considerable potential for design reuse. In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths between 9 and 14.5 um are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS process and implementing a 256 x 256 pixel array on a 30-um pitch. In one of the implemented designs, the feasibility of implementing a 15-um pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal processing allows for a much reduced readout bandwidth requirement with these architectures. To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.
Summary
Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it...
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Lincoln Laboratory high-speed solid-state imager technology
September 17, 2006
Conference Paper
Published in:
SPIE Vol. 6279, 27th Int. Congress on High-Speed Photography and Photonics, 17-22 September 2006, 62791K.
Summary
Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 ¿ 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames per second with readout noise of less than 10 e- rms. An electronic shutter has been integrated into the pixels of the back-illuminated (BI) CCD imagers that give snapshot exposure times of less than 10 ns. For burst imaging, a 5 cm x 5 cm, 512 x 512-element, multi-frame CCD imager that collects four sequential image frames at megahertz rates has been developed for the Los Alamos National Laboratory Dual Axis Radiographic Hydrodynamic Test (DARHT) facility. To operate at fast frame rates with high sensitivity, the imager uses the same electronic shutter technology as the continuously framing 128 x 128 CCD imager. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with ultra-short exposure times (100 to 300 ps). The detector will consist of CMOS readouts for high speed sampling (tens of picoseconds transistor switching times) that are bump bonded to deep-depletion silicon photodiodes. A 64 x 64-pixel CMOS test chip has been designed, fabricated and characterized to investigate the feasibility of making large-format detectors with short, simultaneous exposure times.
Summary
Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 ¿ 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames...
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Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays
August 3, 2005
Conference Paper
Published in:
SPIE Vol. 5902. Focal Plane Arrays for Space Telescopes II, 3-4 August 2005, pp. 1-11.
Summary
The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18- micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.
Summary
The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and...
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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
June 19, 2005
Conference Paper
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Summary
In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
Summary
In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...
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High-speed, electronically shuttered solid-state imager technology
July 8, 2002
Conference Paper
Published in:
Rev. Sci. Instrum. Vol. 74, No. 3, Pt. II, March 2003, pp. 2027-2031 (Proceedings of the 14th Topical Conference on High-Temperature Plasma Diagnostics, 8-11 July 2002)
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Summary
Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cmx5 cm, 512x512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology designed for back-illuminated CCDs. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with short integration times (100 ps to 1 ns). Proposed device architectures use CMOS technology for high speed sampling (tens of picoseconds transistor switching times). Techniques for parallel clock distribution, that triggers the sampling of x-ray photoelectrons, will be described that exploit features of CMOS technology.
Summary
Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cmx5 cm, 512x512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity...
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