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Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-oninsulator devices, combined with a workfunction engineered mid-gap metal gate.

Etching of TiN metal gate materials as a part of an integrated flow to fabricate fully depleted silicon-on-insulator ultralow-power transistors is reported. TiN etching is characterized as a function of source power, bias power, gas composition, and substrate temperature in a high density inductively coupled plasma reactor. Under the conditions used in this work, the TiN etch rate appears to be ion flux limited and exhibits a low ion enhanced etching activation energy of 0.033 eV. Notching of the polysilicon layer above the TiN may occur during the polysilicon overetch step as well as the TiN overetch step. Notching is not significantly affected by charging of the underlying gate dielectric under the conditions used. By optimizing the plasma etch process conditions, TiN:SiO2 selectivity of nearly 1000:1 is achieved, and a two-step TiN main etch and TiN overetch process yields well-defined metal gate structures without severe gate profile artifacts.