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Valleytronics: opportunities, challenges, and paths forward

Summary

A lack of inversion symmetry coupled with the presence of time-reversal symmetry endows 2D transition metal dichalcogenides with individually addressable valleys in momentum space at the K and K' points in the first Brillouin zone. This valley addressability opens up the possibility of using the momentum state of electrons, holes, or excitons as a completely new paradigm in information processing. The opportunities and challenges associated with manipulation of the valley degree of freedom for practical quantum and classical information processing applications were analyzed during the 2017 Workshop on Valleytronic Materials, Architectures, and Devices; this Review presents the major findings of the workshop.
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Summary

A lack of inversion symmetry coupled with the presence of time-reversal symmetry endows 2D transition metal dichalcogenides with individually addressable valleys in momentum space at the K and K' points in the first Brillouin zone. This valley addressability opens up the possibility of using the momentum state of electrons, holes...

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Effect of surface roughness and H-termination chemistry on diamond's semiconducting surface conductance

Summary

The H-terminated surface of diamond when activated with NO2 produces a surface conduction layer that has been used to make FETs. Variations in processing can significantly affect this conduction layer. This article discusses the effect of diamond surface preparation and H termination procedures on surface conduction. Surface preparations that generate a rough surface result in a more conductive surface with the conductivity increasing with surface roughness. We hypothesize that the increase in conductance with roughness is the result of an increase of reactive sites that generate the carriers. Roughening the diamond surface is just one way to generate these sites and the rough surface is believed to be a separate property from the density of surface reactive sites. The presence of C in the H2 plasma used for H termination decreases surface conductance. A simple procedure for NO2 activation is demonstrated. Interpretation of electrical measurements and possible alternatives to activation with NO2 are discussed. Using Kasu's oxidation model for surface conductance as a guide, compounds other than NO2 have been found to activate the diamond surface as well.
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Summary

The H-terminated surface of diamond when activated with NO2 produces a surface conduction layer that has been used to make FETs. Variations in processing can significantly affect this conduction layer. This article discusses the effect of diamond surface preparation and H termination procedures on surface conduction. Surface preparations that generate...

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High-resolution, high-throughput, CMOS-compatible electron beam patterning

Published in:
SPIE Advanced Lithography, 26 February - 2 March 2017.

Summary

Two scanning electron beam lithography (SEBL) patterning processes have been developed, one positive and one negative tone. The processes feature nanometer-scale resolution, chemical amplification for faster throughput, long film life under vacuum, and sufficient etch resistance to enable patterning of a variety of materials with a metal-free (CMOS/MEMS compatible) tool set. These resist processes were developed to address two limitations of conventional SEBL resist processes: (1) low areal throughput and (2) limited compatibility with the traditional microfabrication infrastructure.
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Summary

Two scanning electron beam lithography (SEBL) patterning processes have been developed, one positive and one negative tone. The processes feature nanometer-scale resolution, chemical amplification for faster throughput, long film life under vacuum, and sufficient etch resistance to enable patterning of a variety of materials with a metal-free (CMOS/MEMS compatible) tool...

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Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Published in:
J. Appl. Phys., Vol. 118, No. 4, 2015, 045307.

Summary

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200 x reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.
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Summary

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was...

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Energy efficiency benefits of subthreshold-optimized transistors for digital logic

Published in:
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf. (S3S), 6-9 October 2014.

Summary

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity factor, and the process technology in which the circuit is implemented. For application-specific ICs (ASICs), the minimum energy point usually occurs at a subthreshold supply voltage. Advances in subthreshold circuit design now permit correct circuit operation at, or even below, the minimum energy point. Since energy consumption is proportional to the square of the supply voltage, circuit design techniques and process technology choices that reduce the minimum energy point inherently improve the energy efficiency of ICs. Previous research has shown that optimizing process technology for subthreshold operation can improve IC energy efficiency. This, coupled with the energy efficiency advantages offered by fully-depleted silicon-on-insulator (FDSOI) processes, have led to the development of a subthreshold-optimized FDSOI process at MIT Lincoln Laboratory (MITLL) called xLP (Extreme Low Power). However, to date there has not been a quantitative estimate of the energy efficiency benefit of xLP or other analagous technology for complex digital circuits. This paper will show via simulation that the xLP process technology enables energy efficiency improvements that exceed that of process scaling by one generation. Specifically, the process is shown to improve power delay product by 57% vs. the IBM 90nm low power bulk process, and by 9% vs. the IBM 65 nm low power bulk technology at 0.3V.
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Summary

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity...

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Gadolinium oxide coated fully depleted silicon-on-insulator transistors for thermal neutron dosimetry

Published in:
Nucl. Instrum. Methods Phys. Res. A, Accel., Vol. 721, 2013, pp. 45-9.

Summary

Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd2O3 than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly with neutron dose, consistent with increasing positive charge in the SOI buried oxide layer generated by ionization from high energy 157Gd(n,γ)158Gd conversion electrons. The measured neutron sensitivity is approximately 1/6 the maximum theoretical value, possibly due to electron-hole recombination or conversion electron loss in interconnect wiring above the transistors.
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Summary

Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd2O3 than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly...

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Etching selectivity of indium tin oxide to photoresist in high density chlorine- and ethylene-containing plasmas

Author:
Published in:
J. Vac. Sci. Technol. B, Microelectron. and Nanometer Structures, Vol. 31, No. 2, 13 March 2013, 021210.

Summary

Etching of indium tin oxide (ITO) thin films in high density chlorine plasmas is studied, with the goal of increasing the etching selectivity to photoresist. The ITO etching rate increases with ethylene addition, but is not affected by BCl3 addition. ITO exhibits a threshold energy for ion etching, whereas the photoresist etches spontaneously in chlorine plasmas. The ITO:photoresist selectivity increases with BCl3 addition, ion bombardment energy, and C2H4 addition. It is proposed that the ITO etching rate is limited by desorption of InClx products, and that ethylene addition assists in scavenging oxygen from ITO leaving loosely bound In, which is more easily removed by physical sputtering.
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Summary

Etching of indium tin oxide (ITO) thin films in high density chlorine plasmas is studied, with the goal of increasing the etching selectivity to photoresist. The ITO etching rate increases with ethylene addition, but is not affected by BCl3 addition. ITO exhibits a threshold energy for ion etching, whereas the...

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SOI circuits powered by embedded solar cell

Published in:
2011 IEEE SOI Conf., 3-6 October 2011.

Summary

Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully depleted SOI process on the same wafer. The speed of the ring oscillator increased with increasing light intensity and showed a fastest oscillation with a 4.5 ns stage delay and 0.26 fJ power-delay product. The maximum power generated by the solar cell was 9.6 mW/cm2 with an efficiency of 11.6%.
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Summary

Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully depleted SOI process on the same wafer. The speed of the ring oscillator increased with increasing light intensity and showed a fastest oscillation with a...

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FDSOI process technology for subthreshold-operation ultra-low power electronics

Published in:
ECS Meeting, 1 May 2011 (in: Adv. Semiconductor-on-Insulator Technol. Rel. Phys., Vol. 35, No. 5, 2011, pp. 179-188).
Topic:

Summary

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.
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Summary

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation...

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Work-function-tuned TiN metal gate FDSOI transistors for subthreshold operation

Published in:
IEEE Trans. Electron Devices, Vol. 58, No. 2, February 2011, pp. 419-426.

Summary

The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction inCgd, and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed.
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Summary

The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective...

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