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A hardware root-of-trust design for low-power SoC edge devices

September 22, 2020
  |
Conference Paper
Author:
Alan J. Ehret
…
Published in:
2020 IEEE High Performance Extreme Computing Conf., HPEC, 22-24 September 2020.
Topic:
embedded computing
R&D area:
R&D group:

Summary

In this work, we introduce a hardware root-of-trust architecture for low-power edge devices. An accelerator-based SoC design that includes the hardware root-of-trust architecture is developed. An example application for the device is presented. We examine attacks based on physical access given the significant threat they pose to unattended edge systems. The hardware root-of-trust provides security features to ensure the integrity of the SoC execution environment when deployed in uncontrolled, unattended locations. E-fused boot memory ensures the boot code and other security critical software is not compromised after deployment. Digitally signed programmable instruction memory prevents execution of code from untrusted sources. A programmable finite state machine is used to enforce access policies to device resources even if the application software on the device is compromised. Access policies isolate the execution states of application and security-critical software. The hardware root-of-trust architecture saves energy with a lower hardware overhead than a separate secure enclave while eliminating software attack surfaces for access control policies.
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Summary

In this work, we introduce a hardware root-of-trust architecture for low-power edge devices. An accelerator-based SoC design that includes the hardware root-of-trust architecture is developed. An example application for the device is presented. We examine attacks based on physical access given the significant threat they pose to unattended edge systems...

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A hardware root-of-trust design for low-power SoC edge devices

Fabrication security and trust of domain-specific ASIC processors

May 1, 2017
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Conference Paper
Author:
Mankuan Michael Vai
…
Published in:
IEEE Intl. Symp. on Hardware Oriented Security and Trust, HOST, 1-5 May 2017.
Topic:
algorithms
R&D area:
R&D group:

Summary

Application specific integrated circuits (ASICs) are commonly used to implement high-performance signal-processing systems for high-volume applications, but their high development costs and inflexible nature make ASICs inappropriate for algorithm development and low-volume DoD applications. In addition, the intellectual property (IP) embedded in the ASIC is at risk when fabricated in an untrusted foundry. Lincoln Laboratory has developed a flexible signal-processing architecture to implement a wide range of algorithms within one application domain, for example radar signal processing. In this design methodology, common signal processing kernels such as digital filters, fast Fourier transforms (FFTs), and matrix transformations are implemented as optimized modules, which are interconnected by a programmable wiring fabric that is similar to the interconnect in a field programmable gate array (FPGA). One or more programmable microcontrollers are also embedded in the fabric to sequence the operations. This design methodology, which has been termed a coarse-grained FPGA, has been shown to achieve a near ASIC level of performance. In addition, since the signal processing algorithms are expressed in firmware that is loaded at runtime, the important application details are protected from an unscrupulous foundry.
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Summary

Application specific integrated circuits (ASICs) are commonly used to implement high-performance signal-processing systems for high-volume applications, but their high development costs and inflexible nature make ASICs inappropriate for algorithm development and low-volume DoD applications. In addition, the intellectual property (IP) embedded in the ASIC is at risk when fabricated in...

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Fabrication security and trust of domain-specific ASIC processors

Low power sparse polynomial equalizer (SPEQ) for nonlinear digital compensation of an active anti-alias filter

October 17, 2012
  |
Conference Paper
Author:
Karen M. Gonzalez-Valentin Gettings
…
Published in:
Proc. 2012 IEEE Workshop on Signal Processing Systems, 17-19 October 2012, pp. 249-253.
Topic:
signal processing
R&D area:
R&D group:

Summary

We present an efficient architecture to perform on-chip nonlinear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize power consumption. The architecture was implemented in VHDL and fabricated in CMOS 65 nm technology. Testing results show that undesired spurs are suppressed to near the noise floor, improving the system's spur-free dynamic range by 25 dB in the median case, and consuming less than 12 mW of core power when operating at 200 MHz.
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Summary

We present an efficient architecture to perform on-chip nonlinear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize...

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Low power sparse polynomial equalizer (SPEQ) for nonlinear digital compensation of an active anti-alias filter

On-chip nonlinear digital compensation for RF receiver

September 21, 2011
  |
Conference Paper
Author:
Karen M. Gonzalez-Valentin Gettings
…
Published in:
HPEC 2011: Conf. on High Performance Embedded Computing, 21-22 September 2011.
Topic:
signal processing
R&D area:
R&D group:

Summary

A system-on-chip (SOC) implementation is an attractive solution for size, weight and power (SWaP) restricted applications, such as mobile devices and UAVs. This is partly because the individual parts of the system can be designed for a specific application rather than for a broad range of them, like commercial parts usually must be. Co-design of the analog hardware and digital processing further enhances the benefits of SOC implementations by allowing, for example, nonlinear digital equalization to further enhance the dynamic range of a given front-end component. This paper presents the implementation of nonlinear digital compensation for an active anti-aliasing filter, which is part of a low-power homodyne receiver design. The RF front-end circuitry and the digital compensation will be integrated in the same chip. Co-design allows the front-end to be designed with known dynamic range limitations that will later be compensated by nonlinear equalization. It also allows nonlinear digital compensation architectures matched to specific circuits and dynamic range requirements--while still maintaining some flexibility to deal with process variation--as opposed to higher power general purpose designs.
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Summary

A system-on-chip (SOC) implementation is an attractive solution for size, weight and power (SWaP) restricted applications, such as mobile devices and UAVs. This is partly because the individual parts of the system can be designed for a specific application rather than for a broad range of them, like commercial parts...

READ MORE
On-chip nonlinear digital compensation for RF receiver
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